1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and in particular to a nonvolatile semiconductor memory device provided with a floating gate for storing data based on the state of a charge accumulated in the floating gate.
2. Description of the Related Art
Briefly referring to FIG. 16, a conventional nonvolatile semiconductor memory device of the above-mentioned type will be described. In FIG. 16, symbol SA denotes a sensing amplifier, YD denotes a decoder in a y direction, MC denotes a nonvolatile memory cell, WL1 through WLn denote word lines, BL1 through BLm denote bit lines, and SO denotes a source line for a plurality of nonvolatile memory cell sections including two memory cells MC. The word lines WL1 through WLn are selected by a decoder in an x direction (not shown) perpendicular to the y direction.
FIG. 17 is a circuit diagram of an example of the sensing amplifier SA. An input IN receives the potential of a bit line BLi (i=1, 2, . . . , m) which is selected from the bit lines BL1 through BLm. Symbol V.sub.REF is a prescribed reference potential. Symbol SS denotes a control signal. While the signal SS is low, precharging is performed; and while the signal SS is high, sensing is performed to output a signal DOUT representing memory data.
In such a nonvolatile semiconductor memory device, data is read using the phenomenon that the threshold voltage of a transistor provided in the nonvolatile memory cell changes in accordance with the level of the charge accumulated in a floating gate. In more detail, the voltage on the bit line BL is set to an arbitrary voltage level while the source line SO is grounded. When the voltage level of the word line WL is raised, the charge accumulated in the bit line BL flows out to the source side of the transistor and thus decreases. The threshold voltage of the transistor is determined based on the reduction level in the charge. Thus, data "1" or "0" is read out.
In the above-described circuit, the source line of the transistor should be grounded for reading data. This process requires the transistor to have a source diffusion region and a contact area for supplying a potential to the source diffusion region in a memory cell array. This enlarges the area of the nonvolatile memory device. Further, if the memory cell is in an excessive erase state, the threshold voltage of the transistor becomes negative, and thus a transistor in a memory cell connected to an unselected word line is turned on when the bit line BL is precharged to a prescribed level before the reading operation. Accordingly, it may be impossible to precharge the bit line BL properly, or wrong data may possibly be read since the transistor of the memory cell connected to an unselected word line is "ON" although the transistor of the memory cell connected to a selected word line is "OFF".
The above-mentioned problem will be described in more detail with reference to FIG. 16. An operation by which electrons are injected into a floating gate FG is referred as to a "program operation". By contrast, an operation by which electrons accumulated in the floating gate FG are discharged is referred as to an "erase operation". In the erase operation, it is difficult to control the amount of discharge to be equal to the amount of the accumulated electrons. If the amount of discharge is larger than the amount of the accumulated electrons, holes are generated in the floating gate FG. As the result, the threshold voltage of the transistor of the memory cell MC becomes negative. This state of the memory cell MC is referred to as the "excessive erase state". As an example, the case where the threshold voltages of memory cells A and B in FIG. 16 are normally 5 V and 0.5 V, respectively and the excessive erasure occurs to the memory cell B which results in the threshold voltage of the memory cell B becoming -1 V, is described. Even if the voltage on the WL2, which is connected to a control gate CG of the transistor in the memory cell B is 0 V, the source S and the drain D of the transistor in the memory cell B is electrically connected. That is, the transistor of the memory cell B is in an ON-state even if the memory cell B is in an unselected state. As the result, the level of the voltage applied to BL1 for reading date in the memory cell A is affected by a current through the memory cell B. Accordingly, the data stored in the memory cell A cannot be read correctly.
In order to solve such problems, circuits shown in Japanese Patent Publication No. 5-86675 (Japanese Laid-Open Patent Publication No. 59-147461) have been proposed. In a circuit shown in FIG. 2 of the above publication, when data is read out, the data is changed by carriers, such as hot electrons, which are generated in a floating gate by zener or avalanche breakdown. Accordingly, refreshing of the data is necessary despite the use of the circuit in a nonvolatile memory device. In a circuit shown in FIG. 4 of the above-described publication, a bit line also acts as a control gate, and thus two or more memory cells cannot be arranged on one bit line. In such a structure, data cannot be decoded in the direction of the control gate as is conventionally done, and therefore the memory cell arrays cannot be highly integrated.